TOPIC 2.4

Chip Fabrication & Manufacturing

⏱️26 min read

📚Manufacturing Process

Semiconductor fabrication— the process of transforming ultra-pure silicon wafers into functional integrated circuits containing billions of transistors— represents one of the most complex and capital-intensive manufacturing processes humanity has ever developed. Modern chip fabrication requires extreme precision, working at atomic scales in ultra-clean environments, using equipment that costs hundreds of millions of dollars.

The Silicon Foundation

Silicon Wafer Production and 300mm Standard

The fabrication process begins with silicon wafers— ultra-pure discs of monocrystalline silicon that serve as the substrate for all semiconductor devices. The silicon wafer market is projected at $14.46 billion in 2025, dominated by five companies: Shin-Etsu Chemical (Japan), SUMCO (Japan), GlobalWafers (Taiwan), Siltronic (Germany), and SK Siltron (South Korea).

The industry standard is the 300mm diameter wafer, which accounts for over 63% of the market by revenue in 2024. These wafers are grown from single silicon crystals using the Czochralski process, producing cylindrical ingots that are sliced into thin discs, polished to near-perfect flatness (variations measured in nanometers), and cleaned to semiconductor-grade purity (99.9999999% pure silicon).

Ultra-Pure Materials and Cleanroom Requirements

Modern semiconductor fabs operate as "cleanrooms" with air filtration systems that maintain particle counts orders of magnitude lower than hospital operating rooms— Class 1 cleanrooms allow less than one 0.1-micron particle per cubic foot of air, compared to typical outdoor air containing millions of particles per cubic foot.

Workers wear full-body protective garments ("bunny suits") not to protect themselves, but to protect the wafers from contamination by hair, skin cells, or moisture. A single particle can destroy an entire chip.

🏭 Fab Process Flow

Wafer Preparation

300mm silicon wafer, ultra-pure, polished

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Photolithography

EUV/DUV pattern transfer (repeated 50+ times)

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Deposition & Etching

CVD/PVD layers, plasma etching

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Doping & CMP

Ion implantation, chemical-mechanical polish

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Testing & Packaging

Wafer test, dicing, assembly, final test

2-3 months, 500+ process steps, $15-20B fab facility

Core Fabrication Processes

Photolithography: Patterning at Nanometer Scale

Photolithography is the most critical step, where circuit patterns are transferred onto the wafer using light. The wafer is coated with photoresist (light-sensitive chemical), then exposed through a photomask containing the circuit pattern. This step is repeated dozens of times, with each layer building upon previous ones.

Deposition and Etching: Building 3D Structures

Deposition: Thin layers of materials are deposited onto the wafer with atomic precision. Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD) create layers of conductors (copper, tungsten), insulators (silicon dioxide, silicon nitride), and semiconductor materials. These layers can be just a few atoms thick.

Etching: Unwanted material is precisely removed, carving the patterns defined by photolithography. Plasma etching uses chemically reactive gases to selectively remove material with nanometer precision. This step is critical for creating the three-dimensional structures of modern transistors.

Doping, CMP, and Metrology

Ion Implantation: Dopant atoms (such as boron or phosphorus) are accelerated and implanted into specific regions of the silicon to create the n-type and p-type regions that form transistors.

Chemical-Mechanical Planarization (CMP): The wafer surface is polished flat between layers to ensure subsequent photolithography steps can maintain their precision.

The deposition and etch equipment market is dominated by Applied Materials (US), Lam Research (US), and Tokyo Electron (Japan). Process control is dominated by KLA (US), whose sophisticated tools detect defects at the nanometer scale.

The EUV Revolution

From DUV to EUV: Wavelength Makes the Difference

For years, the industry relied on deep ultraviolet (DUV) lithography at 193nm wavelength. To create features smaller than this wavelength, engineers employed costly multi-patterning— exposing wafers multiple times. This became increasingly difficult below 10 nanometers.

⚡ EUV vs DUV Lithography

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DUV (Old)

Wavelength: 193nm

Min Feature: ~10nm (multi-pattern)

Cost: $50-80M

Complexity: 4-6 exposures/layer

Limit: 7nm node

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EUV (New)

Wavelength: 13.5nm

Min Feature: ~2nm (single)

Cost: $150-400M

Complexity: 1 exposure/layer

Enables: Sub-3nm nodes

EUV's 14x shorter wavelength enables single-exposure patterning at scales impossible with DUV

ASML's Monopoly and High-NA EUV

The solution: Extreme Ultraviolet (EUV) lithography, using light at just 13.5 nanometers wavelength. EUV development took over 30 years and approximately $9 billion in R&D investment from ASML. Each EUV machine costs $150-400 million and requires expert teams to operate.

EUV systems generate 13.5nm wavelength light by focusing a high-powered laser onto tiny droplets of molten tin, creating a plasma that emits EUV photons. These photons are captured by ultra-precise multilayer mirrors and focused onto the wafer. The entire system operates in a vacuum since EUV light is absorbed by air.

By 2025, ASML is delivering next-generation High-NA EUV systems, which increase the numerical aperture to enable even finer feature resolution required for sub-2nm nodes. Each High-NA EUV system costs approximately $370 million and weighs over 150 tons.

Multi-Patterning: The Workaround for Nations Without EUV

ASML's monopoly on EUV has made the company a critical geopolitical player. The Dutch government, under pressure from the US, has restricted exports of EUV systems to China since 2019, effectively limiting China to nodes of 7nm or larger without resorting to expensive DUV multi-patterning workarounds.

Transistor Architectures Across Nodes

Planar Transistors (Through 22nm)

Traditional flat transistor structures where the gate sits atop a flat channel. At smaller scales, these suffered from current leakage due to quantum tunneling effects.

FinFETs: The 3D Breakthrough (22nm-7nm)

Three-dimensional structures where the channel forms a vertical "fin" with the gate wrapping around three sides. This provides superior electrostatic control, dramatically reducing leakage. Developed at Intel in 2011 and later adopted by Samsung and TSMC, FinFETs enabled continued scaling through the 7nm generation.

Gate-All-Around: The 2nm Standard (2025+)

The successor to FinFETs, where the gate completely surrounds the channel on all four sides, providing even tighter control. IBM and Samsung demonstrated 2nm GAA prototypes in 2021, achieving over 300 million transistors per square millimeter.

TSMC's N2 (H2 2025) uses GAA nanosheets, promising 10-15% speed gain or 25-30% power reduction versus N3E
Samsung's SF2 (2025) uses Multi-Bridge-Channel FET (MBCFET), their GAA implementation
Intel's 18A (ramping 2025) uses RibbonFET (Intel's GAA name) combined with PowerVia backside power delivery

Inside a Modern Fab

The $15-20 Billion Facility

Modern semiconductor fabs are among the most expensive structures humanity builds. A leading-edge fab costs $15-20 billion to construct and equip. These facilities operate 24/7/365, with wafers moving through hundreds of process steps in a carefully choreographed ballet coordinated by sophisticated Manufacturing Execution Systems (MES). Each wafer may spend several weeks in the fab, with dozens of layers built up sequentially.

TSMC's Foundry Empire

Taiwan Semiconductor Manufacturing Company (TSMC) is the undisputed leader in advanced semiconductor manufacturing, holding approximately 70.2% of the global foundry market as of Q2 2025. TSMC's dominance stems from consistently being first to market with new nodes, massive R&D investment ($30-40 billion annually), and unmatched manufacturing expertise.

TSMC's Arizona project represents a historic shift. What began as a single $12 billion fab has expanded into a "GIGAFAB cluster" with total investment exceeding $165 billion. However, TSMC acknowledges its operational concentration in Taiwan as a primary risk factor amid rising cross-strait tensions with China.

SMIC's Sanctioned Innovation

Semiconductor Manufacturing International Corporation (SMIC), China's national foundry champion, has made remarkable advances despite stringent US export controls. Denied access to EUV lithography machines, SMIC has ingeniously adapted older DUV immersion lithography tools with complex multi-patterning techniques.

SMIC achieved mass production of a 7nm-class process manufacturing chips for Huawei's Kirin 9000s processor. In 2025, SMIC is reportedly finalizing a 5nm process. This comes at extraordinary economic cost— projected to be 40-50% more expensive than TSMC's EUV-based 5nm node, with yields perhaps only one-third of TSMC's. However, this is a cost the Chinese state is willing to bear, prioritizing technological sovereignty over profit margins.

🎯 Key Takeaways

Modern chip fabrication operates at atomic scales, requiring 300mm ultra-pure silicon wafers, hundreds of process steps over 2-3 months, and Class 1 cleanroom environments cleaner than any hospital
ASML's Extreme Ultraviolet lithography at 13.5nm wavelength "saved Moore's Law," enabling 7nm and below manufacturing, but its monopoly and $150-400M per machine cost created critical geopolitical dependencies
The industry has transitioned from planar transistors (through 22nm) to FinFETs (22nm-7nm, 2011+) to Gate-All-Around nanosheets (2nm, 2025+) with TSMC, Samsung, and Intel all deploying GAA in 2025
TSMC holds 70.2% foundry market share with technological leadership at every advanced node, operating $15-20B fabs that run 24/7, and expanding with $165B+ Arizona investment despite Taiwan concentration risks

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